Measurement system internal interfaces

2.1SPI interface

The two controllers communicate with the sbRIO with two separate SPI buses that can run at clock rates of up to 18MHz. The microcontrollers are configured as slaves. They can activate an interrupt line in order to force FPGA of sbRIO (which is master) to retrieve microcontroller data. The data size is always 16 bit (referenced as one word).

2.1.1Transmission protocol

The following communication protocol is used for communication in both directions (FPGA to microcontroller, microcontroller to FPGA).

It must be noticed that only the low byte of the data area is used. The high byte always contains the constant 0x40 for data messages (except data word 0, which contains the command byte additionally) or 0x80 for status messages (compatibility reasons, FPGA discards received data words with a value less or equal to 0x00FF). A data word with a value of 0x0000 will be added automatically by the microcontroller in order to clear its SPI buffer.

2.1.2Status codes

Each command received from sbRIO will be answered by the microcontroller. This can be done by a data message (which contains application data processed by RT/PC) or a status message. It is possible to deactivate this functionality by command.

The following status codes are defined.

2.1.3Command description

The latest descriptions can be found in the VI documentation.

2.2Non-volatile storage of data

The on-board data flash of the two STM32 can be used as an EEPROM for the non-volatile storage of data (for example baud rates, ID filter settings, termination resistances …).

2.3Analog Input

The interface of the analog input board consists of

• 3 address buses for multiplexing the analog channels for every analog group separately
• Signals for the serial communication with the ADCs.
• Serial interface to the EEPROM for calibration data.

2.3.1Multiplexers

As shown in the functional block diagram, the channels are multiplexed to ADCs with two channels each. 32 single-ended channels are handled by a 32:1 multiplexer with address lines ADR1_0 to ADR1_4, the remaining 16 single-ended channels are handled by a 16:1 multiplexer with address lines ADR2_0 to ADR2_3 and the differential channels are switched using two 8:1 multiplexers with shared address lines ADR3_0 to ADR3_2.

All address lines are buffered using high-speed CMOS buffers to reduce the load for the FPGA output drivers and to provide clean signals on the PCB.

The address lines are switched during the ADC hold phase to avoid influencing the conversion results.

The inputs are sampled by the internal Sample & Hold stage of the ADCs between the 32nd rising edge of SCK and the rising edge of CONV.

2.3.2ADCs

Both ADCs are clocked by the same CONV and SCK signals.

The ADC outputs are buffered using high-speed CMOS buffers to drive the ribbon cable’s capacitance.

2.3.3EEPROM

The EEPROM contains an ID to identify the PCB as an analog measurement card, the type (128 or 64 channel version), a calibration timestamp and the hardware version. Furthermore offset and gain calibration data for each channel is stored as well as the input voltage scaling factor according to the resistor dividers on the PCB. There is an EEPROM present for every analog subsystem respectively. Following table shows an excerpt of the EEPROM content. A detailed memory map can be found in the separate file “EEPROM Memory Map Analog_LDSA.xlsx”.

2.4Digital output

As shown in the block diagram, the relays can be accessed via two I²C port expanders. All pins are configured as inputs at power-up and must be reconfigured as outputs before the relays can be switched.

Addresses for write access:

• Port expander 1 (relays 01 to 15): 0b11101000 = 0xE8
• Port expander 2 (relays 16 to 32): 0b11101100 = 0xEC
• Port expander 3 (relays 33 to 48): 0b11101110 = 0xEE
• Port expander 4 (relays 49 to 64): 0b11101010 = 0xEA

The LSB is set to zero for write access.

Write to output ports:

Write to configuration registers: