HW Description

1.1Block Diagram

The Measurement system contains the following:

• NI Single-board-RIO sbRIO-9602 (COTS from National Instruments) including
  • Processor with real-time Software (LabVIEW RT)
  • FPGA for accessing other boards via digital IO and data processing (LabVIEW FPGA)
• 128x Analog inputs with the following configuration twice:
  • 32 channels single ended (0…32V / 14Bit)
    • 3kS/s parallel / 1,2MS/s single channel
    • referenced to a GND node
  • 16 channels single ended (0…32V / 14Bit )
    • 6kS/s parallel / 1,2MS/s single channel
    • referenced to an additional GND node
  • 16 channels differential (+-48V / 14 Bit )
    • 150kS/s parallel / 1,2MS/s single channel
• 88x digital outputs with the following configuration twice:
  • 24 relays shutters
  • 8 relays changeover
  • 10 FET outputs referenced to system GND
  • 2 FET outputs isolated for any reference GND
• 4x CAN
  • 2x high speed with selectable termination resistor (None, 120 Ohm, 60 Ohm)
  • 2x without transceiver to implement DUT specific Transceiver in the load-box for high speed, low speed, or special CAN (e.g. E-CAN for trucks)
• 10x serial
  • without transceiver to implement DUT specific Transceiver in the load-box for K-Line, LIN, …
• LVDS interface (3x Out, 2x In) for up to 6 cascaded current measurement modules
• 16x open collector output for controlling status LEDs or general purpose output
• 6x digital input for high speed digital signal capturing
• 16x digital IO for low speed digital signal capturing or generation

1.2Power Supply

The Measurement system needs a single 24V DC supply at a current consumption of approx. 700mA in average, 1500mA maximum.

1.3Internal Interfaces

In the standard configuration the measurement system consists of an aluminium carrier which contains 4 printed circuit boards. These are:

• NI Single board RIO board sbRIO-9602 (COTS from National Instruments)
• Base and communication–board (board developed by IRS)
• Digital output board (board developed by IRS)
• Analogue Input board (board developed by IRS)

The following figure illustrates the 4 boards inside the measurement system

The boards are connected with ribbon cables to the headers P2, P3, P4, and P5 of the sbRIO device. Additionally up to three Compact-RIO c-Series modules can be attached according to the following picture.

For accessing the c-Series external signals the c-Series signals can be routed to a spare 96 pol. connector (DIN41612) on the base and communication board.

1.4External Interfaces

All external connections to the DUT and the load-box are established via 6x 96pol. VG connectors (DIN41612). I.e. the carrier can be plugged into the load-box without any other cabling. The connection for communication with the PC is the only additional cable, which is actually a common Ethernet connection with a standard Ethernet cable.

The following block diagram shows a typical setup of the measurement system within a lifetime tester, where additional signal conditioning can be applied for non-standard voltage ranges, load current measurements, analogue outputs, and communication transceivers.

1.5Load box design

The following figure illustrates the typical placement of the measurement system inside the load box from the side view:

In the typical application of the measurement system the artificial and original loads of the DUT are placed in the front area of the load-box, mounted on heat sinks or other load cards. At the backside the measurement system should be placed with additional electronics like current measurement module, and the connectors to DUT and power supply.

The following figure illustrates the typical placement of the measurement system inside the load box from the top view:

The following figure illustrates the typical placement of the measurement system inside the load box from the top view:

As illustrated in the following figures the measurement system can be plugged into the DUT specific load box

Following figure shows the alignment and dimensions of the VG-Connectors, where the correct placement may be found by counting “holes” on the mounting rail:

1.6GND Concept

One important issue is the GND concept, when running lifetime testers. MesSy provides a system GND, to which all internal signals and nearly all digital user channels refer to. For analog measurements additional GND reference inputs are available.

1.6.1Digital GND references

Nearly all digital signals are referenced to System-GND, which is determined by the 24V power supply. Voltage drops are usually less problematic for digital signals, but they should be taken into account.

Following figure illustrates the GND concept of the MesSy and its digital channels:

1.6.2Analog GND references for measurement

The GND references for analog measurements are an important issue, since voltages may vary due to voltage drop on the wiring harness. Because of this, analog inputs may be referenced to different voltage levels. These signal levels may vary up to 2,7V over the MesSy system GND, determined by the 24V power supply.

Different reference inputs may also be used to reference the voltage measurements to different DUTs or different GND Pins of one or more DUTs.

Note, that for differential inputs the reference inputs are not relevant, since every channel has its own reference.

1.7Base and communication board

The base and communication card was designed as a carrier and communication board for the sbRIO. Apart from the supply and mounting holes for the sbRIO, it provides

• a total of four CAN channels, with transceiver enable
• up to 10 serial interfaces, with transceiver enable
• 16 open-collector outputs,
• 16 TTL- and CMOS compatible general-purpose IOs,
• three LVDS outputs and two LVDS inputs for communication with the current measurement modules
• I²C interface for external electronic modules.
• 3 slots for extensions with NI Compact-RIO c-Series modules

Two microcontrollers with ARM Cortex M3 core are used to provide CAN and serial interfaces; both are used in identical circuits and have separate communication busses as well as separate reset signals to the sbRIO. Deep FIFO buffers for transmission and reception on each interface make sure that no data is lost even when all interfaces are heavily used simultaneously.

1.7.1Block Diagram

1.7.2Specifications

CAN communication

For CAN communication there are 4 CAN channels on the board, distributed on two microcontrollers. One CAN channel of each controller is configured as high-speed and offers software-configurable termination (open/120 Ohm/60 Ohm) by means of reed relays. The other channel has to be connected externally to high- or low-speed transceivers with corresponding termination.

Serial and CAN communication lines with external transceivers

For each of the serial interfaces, three pins are connected to the VG connector: RX, TX and Enable. This allows the external connection of transceiver ICs (RS232, LIN, K-Line, discrete level converters) which can be deactivated using the enable signal. All serial interface and CAN signals for external transceivers meet the following specification

General Purpose IOs Trig 1…16

16 general purpose IOs are available via an I2C port expander. All IOs are protected with series resistors of 220 Ohm. The interrupt pin of the port expander is connected to the sbRIO to allow fast reaction to changing inputs. The general-purpose IOs are provided via an I²C port expander.

Open Collector Outputs 1…16

The open-collector outputs can sink currents up to 400mA each, limited by the maximum current carrying capacity of the copper traces.

If more than one pin per driver IC is used, the maximum allowable current decreases. The figure below shows the de-rating curve if all outputs are used: at 25°C, 125mA per pin are allowed, at 85°C about 60mA.

LVDS Interface for CMM

There are three TX lines and two RX lines available for interfacing with LVDS devices like the Current measurement module CMM_II. The copper traces have been routed with a differential impedance of approximately 100 Ohm and the RX lines are terminated with 100 Ohm resistors.

The copper traces have a width of 350µm and a thickness of 35µm. For epsilon_r=4.2 and 475µm prepreg height, the characteristic impedance of a single trace is about 80 Ohm. A differentially routed pair of these traces with a distance of 150µm has a differential impedance of 103 Ohm.

General purpose high speed inputs

Six TTL- and CMOS compatible inputs are available which are buffered with a high-speed CMOS buffer and can be used for the acquisition of fast digital signals. The 6 high-speed inputs are protected with a series resistance of 1 kOhm and double schottky diodes. A 100 kOhm pull-down resistor ensures a defined potential, if the inputs are left open. Signals with both 3.3V and 5V voltage level can be connected.

I²C-Interface

The I²C can be used to control additional external electronic modules.

C-Series modules

Three C-Series modules can be connected to the three Sub-D connectors of the sbRIO to add further functionality

Microcontroller Flash interface

This interface is used for flashing the Microcontrollers in the self test adapter. This interface is only for IRS internal use.

1.7.3Layout

1.7.4Connection to sbRIO

The communication board is connected to sbRIO header P2 via a 50 way connector with the following pin assignments.

1.7.5Pinning VG connector X1 (external signals)

1.7.6Pinning VG connector X2 (Power supply, Microcontroller Flashing, Reserved)

Pins C24 to C31 are used for Microcontroller flashing. This procedure is only performed at IRS. Do not connect any signals to these pins.

Pins B23 and C23 are used for connection of additional external modules via I²C. For using the I²C-interface refer to chapter 4.5.

The rest of the second VG connector X2 is almost entirely reserved for future use, especially for the wiring to additional C-series modules, which can be attached to the RIO via three SUB-D connectors and their inputs can be wired to the VG connector. All of the VG connector’s pins have been routed to three 32-way headers for this purpose.

1.7.7Communication line relations

Note, that there are two microcontrollers, which handle both 2 CAN interfaces and 5 serial interfaces, respectively. The following communication lines are assigned to the two microcontrollers according to the following table:

1.7.8CMM connection

For connection of the CMM, please refer to chapter 4.1.

1.8Analog input board 128x

The analog input board provides 128 analog channels divided into two identical 64-channel subsystems with the following properties:

• 32 single-ended channels (external reference voltage 1), 0...32V @ 3 kS/s simultaneously
• 16 single-ended channels (external reference voltage 2) , 0...32V@ 6 kS/s simultaneously
• 16 differential channels, subdivided in simultaneously sampled groups of 8 channels each, -48...48V @ 150 kS/s in parallel.

To keep input currents as low as possible, no voltage divider was placed at the input of the single-ended channels. By connecting the signal directly to the non-inverting input of the input amplifier, very high input impedance is achieved. It should be noted that this open input causes the amplifiers to drift to the upper supply rail if no input voltage is connected. In this case, the ADCs return all ones (0x3FFF).

An EEPROM memory is provided that can be used to store calibration data, calibration values, an ID, the hardware revision and technical details (e.g. attenuation / gain of each channel).

The analog input board is supplied by a single 24V DC supply as the whole measurement system. A switch mode power supply between the analog measurement subsystems generates positive and negative voltages and LDOs are used for linear regulation of these voltages to provide clean supply rails. Following figure illustrates the power supply unit of the analog input board.

Soft start / power sequencing is included to reduce the inrush current at the moment the power supply is connected.

As shown in the following functional block diagram, the channels are multiplexed to ADCs with two channels each. 32 single-ended channels are handled by a 32:1 multiplexer with address lines ADR1_0 to ADR1_4, the remaining 16 single-ended channels are handled by a 16:1 multiplexer with address lines ADR2_0 to ADR2_3 and the differential channels are switched using two 8:1 multiplexers with shared address lines ADR3_0 to ADR3_2.

All address lines are buffered using high-speed CMOS buffers to reduce the load for the FPGA output drivers and to provide clean signals on the PCB.

1.8.1Block diagram

1.8.2Specifications

All inputs are converted with a resolution of 14 bits.

The single-ended inputs can be sampled at a rate of 3kSa/s (channels 1-32 and 65-80) / 6kSa/s (channels 33-48 and 81 to 96) each, the differential inputs at more than 150kS/s.

If only one channel is measured, sampling rates of up to 1.2 MSa/s (possibly 1.5MSa) can be achieved.

The differential inputs are frequency-compensated for accurate waveform reproduction.

Specification of single-ended channels

Specification of differential channels

1.8.3Layout

1.8.4Connection to sbRIO

The card is connected to sbRIO P4 and P5 via two 50 way connectors with the following pin assignment respectively

1.8.5Pinning VG connector X3 (external signals Analog subsystem 1)

SING_In_1-SING_In_32 are referenced to REF_In_1, SING_In_33-SING_In_48 are referenced to REF_In_2.

1.8.6Pinning VG connector X4 (external signals Analog subsystem 2)

SING_In_1-SING_In_32 are referenced to REF_In_1, SING_In_33-SING_In_48 are referenced to REF_In_2.

The reference inputs are protected against signals of more than 2.7V above or 0.2V below ground but this range may only be exceeded for short periods of time!

The +24V supply will be connected to pins C12 & C13 of each VG-connector.

1.8.7Analog Accuracy

To obtain good accuracy a calibration procedure has to be performed. The gain and offset of every channel have to be determined after build-up. The gain and offset values are stored in the EEPROM of the analog input board. They are read at startup, and are used for every analog read out.

Single-ended channels

Following figure shows the typical accuracy of all 96 single ended channels not calibrated

Following figure shows the typical accuracy of all 96 single ended channels after calibration

Differential channels

Following figure shows the typical accuracy of all 32 differential channels, not calibrated.

Following figure shows the typical accuracy of all 32 differential channels after calibration

1.9Digital Output board

The digital output card provides 64 relays and 24 MOSFETs for general switching purposes. The relays are divided into 48 shutters and 16 changers. The MOSFETs are connected as open-drain low side switches and can handle up to 60V and 3A. However, the VG connector is only specified for 2A per pin so a current of 2A should not be exceeded. The overall current of all 10 FETs that switch to GND should be kept below 14A.

4 of the 24 transistors are galvanically isolated from the rest (and from each other).

The MOSFETs can each be switched directly from I/O pins of the sbRIO: a logical 0 turns the MOSFET on, a logical 1 off. Every MOSFET output may be used for fast switching applications as PWM.

The relays have to be accessed through I²C port expanders. All port expanders are connected to the same I²C bus but have different addresses. The port expanders switch the relays with help of powerful driver ICs.

The Relais_FET_LDSA card consists of two identical subsystems. The MOSFET part and the port expanders of the card are powered from the sbRIO; the relays need an additional 24V supply on the VG connectors X5, X6.

1.9.1Block Diagram

A functional block diagram is shown below that illustrates how each of the subsystems works (i.e. one half of the total system).

1.9.2Specifications

Open Drain MOSFET Outputs

Relays- Shutters

Relays- Changeover

Following figure shows the maximum switching voltage, dependent on the switching current of the changeover relays.

1.9.3Layout

1.9.4Connection to sbRIO

The card is connected to sbRIO header P3 via a 50 way ribbon cable. The corresponding connector has the following pin assignments. Make sure the card is not connected to any other connector than P3 of the sbRIO!

1.9.5Pinning VG connector X5 (external signals digital subsystem 1)

The open-drain outputs 1 to 10 all switch to GND while the isolated open-drain 11 and 12 switch to separate pins (GND_ISO_11 and GND_ISO_12).

1.9.6Pinning VG connector X6 (external signals digital subsystem 2)

The open-drain outputs 12 to 22 all switch to GND while the isolated open-drain 23 and 24 switch to separate pins (GND_ISO_23 and GND_ISO_24).

1.9.7PWM timing with MOSFETs

All Open Drain outputs, including the isolated ones, can be used for PWM generation.

The following figure shows the typical timing behaviour of a MOSFET output with an external pull-up of 1 kOhm connected

Note that with pull-up resistors of higher resistance, higher rise times will occur. The fall time is quite independent of the pull-up resistor size.

The sbRIO-SW uses a timing resolution of 1µs. If necessary, the resolution can be adjusted up to 25ns. But note, that this would reduce maximum period of signal generation.