# PC Software

URL: https://irs.systems/en/docs/resolver-simulation/pc-software

The Software for PC is mostly for demonstrations and test purposes only, however many of its components (vi’s) can be used also in own software implementations. This makes the developing of customer applications faster and easier.

Note: The PC software included in this project is not suitable for direct FPGA control without using the real time system!

## Execution of demo software

To start the software there are two possibilities available. The first approach is to open the desired top vi (“PC_ResSi_Top.vi” or “PC_RVDT_Top.vi”) and push the run button. The second possibility is to build the predefined build specification (if not already done) and then to start the compiled executable located in sub folder “PC_EXE”. The advantage of second method is that it needs just the run time installed on the target machine.

## Resolver simulation

Not described in manual V3.0. See [Resolver Mode Software](/en/docs/resolver-simulation/resolver-mode-software) (from manual V2.2).

## RVDT simulation

### Demo & Test GUI

<figure>
  <img src="/docs/assets/resolver-simulation/images/ressi-pc-rvdt-gui.png" alt="PC_RVDT_Top.vi front panel with areas 1 to 4">
  <figcaption>Figure 23: PC&#95;RVDT&#95;Top.vi – GUI</figcaption>
</figure>

1. Basic configuration
   - Target IP / Hostname -> RIO target address
   - FPGA Versions (Date) -> FPGA compile date (Format: YYYYMMDD)
   - Channel Number -> Current selected channel to control
2. Angle Control
   - Angle [°] -> Desired simulation angle in degree
   - Set / Update -> Start moving to position defined by “Angle [°]”
   - Act. Angle [°] -> Actual simulation position in degree
3. Device Setup
   - Set Config. -> Write configuration to target
   - Get Config. -> Read current configuration from target
   - Save Config. -> Save current configuration permanently to target flash memory
   - Max. Angle [°] -> Maximum angle swing (see [Control interface](/en/docs/resolver-simulation/real-time-system#control-interface-rvdt-variables))
   - Angle Speed [°/sec] -> Moving speed to new angle position (see [Control interface](/en/docs/resolver-simulation/real-time-system#control-interface-rvdt-variables))
   - Amp. Transfer Factor -> Transfer factor between excitation signal and differential output signal
   - Calibration -> Calibration settings (see [Control interface](/en/docs/resolver-simulation/real-time-system#control-interface-rvdt-variables) > RT_PC_RVDT_LUT_Calibration.ctl)
4. Application Control

### VIs for integration into user application

There are some vi’s for communicating with the real time system. These vi’s can be used in any user application:

- **PC_RVDT_FPGAVersion.vi** -> Read the FPGA compilation date

![Connector pane of PC_RVDT_FPGAVersion.vi](/docs/assets/resolver-simulation/images/ressi-vi-fpgaversion.png)

- **PC_RVDT_SetAngle.vi** -> Set new simulation angle

![Connector pane of PC_RVDT_SetAngle.vi](/docs/assets/resolver-simulation/images/ressi-vi-setangle.png)

- **PC_RVDT_GetStatus.vi** -> Read current status (actual angle)

![Connector pane of PC_RVDT_GetStatus.vi](/docs/assets/resolver-simulation/images/ressi-vi-getstatus.png)

- **PC_RVDT_GetConfig.vi** -> Get current configuration

![Connector pane of PC_RVDT_GetConfig.vi](/docs/assets/resolver-simulation/images/ressi-vi-getconfig.png)

- **PC_RVDT_SetConfig.vi** -> Set a new configuration

![Connector pane of PC_RVDT_SetConfig.vi](/docs/assets/resolver-simulation/images/ressi-vi-setconfig.png)

- **PC_RVDT_SaveConfig.vi** -> Save configuration permanently to flash memory (boot config)

![Connector pane of PC_RVDT_SaveConfig.vi](/docs/assets/resolver-simulation/images/ressi-vi-saveconfig.png)